1. Field of the Invention
The invention in general relates to integrated circuit memories and more particularly to a fast sense amplifier incorporated into such circuits.
2. Statement of the Problem
Integrated circuit memories generally contain a two dimensional array of storage cells arranged in rows and columns. As is well-known, integrated circuit memories are generally mass produced by fabricating hundreds of identical circuit patterns on a single semiconducting wafer, which wafer is subsequently sawed into hundreds of identical dies or chips. The advantages of building integrated circuits with smaller individual circuit elements so that more and more circuitry may be packed on a single chip are well-known: electronic equipment becomes less bulky, reliability is improved by reducing the number of solder or plug connections, assembly and packaging costs are minimized, and improved circuit performance, in particular higher clock speeds. However, the smaller the size of the individual cell, the smaller the size of the individual electrical components in the cell, and the smaller the electrical signals associated with them. Thus the signals produced by individual cells are much too small to be used by external circuitry. Thus, sense amplifiers are generally built into memory integrated circuits to sense the signals and to amplify them to a level where they can be utilized by an external circuit. In order to amplify the signal sufficiently, prior art memory sense amplifiers have generally included two or more stages of amplification. Since amplifier circuits generally only provide a certain gain to a signal, and the input signal can vary, the particular voltage levels of the output signals are not generally a constant voltage. Thus the amplifier stages are generally followed by an invertor stage to "drive the voltage to the rails", that is, to drive the voltage to the full voltage differential of the external circuit. Generally, integrated circuits are binary logic circuits, where the voltages represent complementary logic values that are alternately referred to as "true and false", "logic 1 and logic 0", or "logic high and logic low", the latter of which shall generally be used herein. Finally, sense amplifiers often will have an output stage that produces a tristate output: i.e. high, low and off, since this allows individual circuits to be tied together.
As more, and more individual storage cells are placed onto a single chip, the length of the electrical lines connecting the individual cells to the amplifiers becomes longer and longer as compared to the individual cell size, and the capacitance associated with the lines becomes larger. This combination of small signals and lines with large associated capacitance results in long times for useful signal levels to rise on the lines. As is well known, speed is an important factor in such memories, since the faster the cells can be read, the faster is the computer of which the memory is a part, and the more operations the computer can do. Thus in order to enhance the speed of reading cells, memory sense amplifiers must be very fast. However, as is well known in the art, to be fast, transistors generally must be relatively large. Thus transistors used in the sense amplifier circuits are typically larger than the transistors in the individual cells and thus occupy a significantly larger part of the integrated circuit. Thus sense amplifier circuits that include two or mores stages of amplification plus an invertor stage can significantly increase the integrated circuit size. Therefore there is a need for a sense amplifier circuit that can drive the voltage to the rails and yet is relatively simple.
Moreover, each stage in an amplifier adds additional response time, since it takes time for the logic of each stage to rise to full voltage. Thus it would be highly desirable to have a sense amplifier that could push the voltage to the rails in two or less stages.
For many applications of integrated circuit memories, such as for portable computers and other battery powered intelligent devices, the amount of power available is limited. Thus it is important that sense amplifiers not only are fast and small, but also consume a minimum of current. Thus many sense amplifiers are designed to be in an "off" or no-current-drain condition when data is not being read.
However, this means that the amplifier must come "on" before it can read the signals. This again takes time. Thus it would be highly desirable to have a sense amplifier that can quickly push a voltage to the rails from a no-current-drain condition.
The sense amplifier according to the invention shall be illustrated as implemented in a static random access memory (SRAM), which is a common type of integrated circuit memory. The cells in SRAM circuits are arranged in an array of rows and columns with all the cells in a given column connected to an electrical line called the bit line. Each cell contains a flip-flop, and data is stored in the cell by latching the flip-flop in either a logic 0 or a logic 1 state. When a read signal is input to the array requesting the data in a particular cell, the data is read out as either a logic 0 or a logic 1 on the bit line associated with the particular cell. In a SRAM each bit line is actually a pair of complementary lines, that is a "positive" or "logic 1" line and a "negative" or "logic 0" line, and the differential signal between the lines is read to determine the state of the flip-flop. Sense amplifiers have long been incorporated into SRAM memories to read these differential signals, and a common design is to include one sense amplifier per bit line pair, that is, per column in the array. Or decoders may be built into the circuit each of which connects a pair of bus lines associated with the decoder to any one of a multiple of bit lines, with one sense amplifier associated with each decoder. Whatever the particular design, there is a need for a simple, fast SRAM sense amplifier that can push the differential voltage on the associated bit or bus line to the rails in one or two stages from a no-current-drain status.
3. Solution to the problem
The present invention solves the above problems by providing a sense amplifier that drives the voltage to the rails in two or less stages.
The invention in addition provides a sense amplifier that can drive the voltage to the rails very quickly from a no-current-drain condition. It can in fact provide an output useable by an external device within 2 ns of a typical cell-level signal being provided at the input, which is 1 ns to 3 ns faster than prior art sense amplifiers.
The invention provides the above features by utilizing a clocked latch rather than a second stage of amplifier. That is, in an SRAM, the time when a cell read signal will be arriving at the inputs of the sense amplifier, is always accurately known, since the output is in response to a READ signal received by the SRAM. Further, computers and computer memories always operate according to well-defined clock cycles, and the read signal always arrives a well-defined time in the clock cycle. The invention uses the read timing signals to permit the latch to remain in a low logic level, no-current-drain state when no signal is being sensed and precharges the latch just prior to a signal arriving, which in effect, causes the latch to begin the process of setting itself even before the signal on the input line is large enough for the sense amplifier to produce a useable output.
The invention also accomplishes the above features by providing a sense amplifier circuit in which the pair of output signals begin to rise from a zero voltage before a full input signal is available. The pair of signals rise together to about half the full voltage before the input signal causes them to separate, and go to the rails, with one falling to zero and the other rising to the full system voltage. Thus, to produce the desired output signal difference, the individual signals must only change by half as much as one of them would have had to change if they had started at zero when the input signal had reached a value high enough to trigger the sense amplifier.